View ADSST-EM-3035_1109226.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
FEATURES IEC 687, Class 0.5 and Class 0.2 Accuracy ANSI C12.1 IEC 1268, Requirements for Reactive Power Configurable as Import/Export or Import Only Simultaneous Measurement of: Active Power and Energy--Import and Export Reactive Power and Energy Apparent Power Power Factor for Individual Phases and Total Frequency RMS Voltage for All Phases RMS Current for All Phases Harmonic Analysis for Voltage and Current All Odd Harmonics up to 21st Order Interface with a General Purpose Microcontroller User-Friendly Calibration of Gain Offset and Phase and Nonlinearity Compensation on CTs (Patent Pending) Two Programmable Output E-Pulses Programmable E-Pulse Constant from 1,000 Pulses/kWh to 20,000 Pulses/kWh 15 kHz Sampling Frequency Tamper-Proof Metering Single 5 V Supply GENERAL DESCRIPTION
SMPS RESISTOR BLOCK
SALEM Three-Phase Electronic Energy Meter ADSST-EM-3035
FUNCTIONAL BLOCK DIAGRAM
LCD DISPLAY
(R)
DSP SPI BUS C
ADC BUTTONS CT CT CT
ADSST-EM-3035 CHIPSET
FLASH
OPTO
RTC
RS-232
The ADSST-EM-3035 Chipset consists of a fast and accurate 6 channel, 16-bit sigma-delta analog-to-digital converter ADSST-73360AR (ADC), an efficient digital signal processor ADSST-2185KST-133 (DSP), and Metering Software. The ADC and DSP are interfaced together to simultaneously acquire voltage and current samples on all the three phases and perform mathematically intensive computations to accurately calculate the Powers, Energies, Instantaneous Quantities, and Harmonics. The chipset could be interfaced to any general-purpose microprocessor to develop state of the art polyphase or Tri-vector energy metering solution in accordance with IEC 1036, IEC 687, or ANSI C12.1. All calibrations are done in digital domain and no trimming potentiometers are required.
SALEM is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
ADSST-EM-3035
ADSST-2185KST-133 (DSP) SPECIFICATION FEATURES 30 ns Instruction Cycle 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch Three-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 100 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode ADSP-2100 Family Code Compatible, with Instruction Set Extensions 40 kBytes of On-Chip RAM, Configured as 8 KWords On-Chip Program Memory RAM and 8 KWords On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead TQFP 16-Bit Internal DMA Port for High Speed Access to OnChip Memory (Mode Selectable) 4 MBytes Byte Memory Interface for Storage of Data Tables and Program Overlays 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable) Programmable Memory Strobe and Separate I/O Memory Space Permits Glueless System Design (Mode Selectable) Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE-Port Emulator Interface Supports Debugging in Final Systems GENERAL DESCRIPTION
The ADSST-2185KST-133 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSST-2185KST-133 combines the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The ADSST-2185KST-133 integrates 40 kBytes of on-chip memory configured as 8 Kwords (24-bit) of program RAM and 8 Kwords (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSST-2185KST-133 is available in a 100-lead TQFP package. In addition, the ADSST-2185KST-133 supports instructions that include bit manipulations, bit set, bit clear, bit toggle, bit test new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory transfers, and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSST-2185KST-133 operates with a 25 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSST-2185KST-133's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, the ADSST-2185KST-133 can:
* * * * * *
Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation This takes place while the processor continues to: Receive and transmit data through the two serial ports Receive and/or transmit data through the internal DMA port Receive and/or transmit data through the byte DMA port Decrement timer
POWER-DOWN CONTROL DATA ADDRESS GENERATORS DAG 1 DAG 2 MEMORY PROGRAM SEQUENCER 16K 24 PROGRAM MEMORY 16K 16 DATA MEMORY PROGRAMMABLE I/O AND FLAGS FULL MEMORY MODE EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER
PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
EXTERNAL DATA BUS ARITHMETIC UNITS ALU MAC SHIFTER SERIAL PORTS SPORT0 SPORT 1 TIMER INTERNAL DMA PORT HOST MODE
ADSP-2100 BASE ARCHITECTURE
Figure 1. Functional Block Diagram
-2-
REV. 0
ADSST-EM-3035
ARCHITECTURE OVERVIEW
The ADSST-2185KST-133 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSST-2185KST-133 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. Figure 1 is an overall block diagram of the ADSST-2185KST-133. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. The shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. The internal result (R) bus connects the computational units so the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. With internal loop counters and loop stacks, the ADSST-2185KST-133 executes looped code with zero overhead. No explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from data memory and program memory. Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is postmodified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Efficient data transfer is achieved with the use of five internal buses: * Program Memory Address (PMA) Bus * Program Memory Data (PMD) Bus * Data Memory Address (DMA) Bus * Data Memory Data (DMD) Bus * Result (R) Bus The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting the ADSST-2185KST-133 to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSST-2185KST-133 can fetch an operand from program memory and the next instruction in the same cycle.
An interface to low cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the ADSST-2185KST-133 to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. The ADSST-2185KST-133 can respond to 11 interrupts. There are up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port, and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. The ADSST-2185KST-133 provides up to 13 general purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). Serial Ports The ADSST-2185KST-133 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSST-2185KST-133 SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User's Manual, Third Edition.
* SPORTs are bidirectional and have a separate, double-buffered
transmit and receive section.
* SPORTs can use an external serial clock or generate their own
serial clock internally.
* SPORTs have independent framing for the receive and transmit
sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings.
* SPORTs support serial data word lengths from 3 to 16 bits and
provide optional A-law and M-law companding according to CCITT recommendation G.711.
* SPORT receive and transmit sections can generate unique
interrupts on completing a data-word transfer. SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data-word. An interrupt is generated after a data buffer transfer.
When configured in host mode, the ADSST-2185KST-133 has a 16-bit Internal DMA port (IDMA port) for connection to * external systems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSP's on-chip program and data RAM. REV. 0 -3-
ADSST-EM-3035
* SPORT0 has a multichannel interface to selectively receive and
transmit a 24- or 32-word, time-division multiplexed, serial bitstream.
Pin Descriptions
* SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration.
The ADSST-2185KST-133 is available in a 100-lead TQFP package. To maintain maximum functionality and reduce package size and pin count, some serial ports, programmable flags, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.
Table I. Common-Mode Pins
Pin Name(s) RESET BR BG BGH DMS PMS IOMS BMS CMS RD WR
IRQ2+PF7 IRQL0+PF5 IRQL1+PF6 IRQE+PF4
Number Input/ of Pins Output Function 1 1 1 1 1 1 1 1 1 1 1 1
1
Pin Name(s)
Number Input/ of Pins Output Function I I O I/O I/O Mode Select Input-Checked only During RESET Clock or Quartz Crystal Input Processor Clock Output Serial Port I/O Pins Serial Port I/O Pins Edge- or Level-Sensitive Interrupts Flag In, Flag Out2 Power-Down Control Input Power-Down Control Output Output Flags VDD and GND
I I O O O O O O O O O I
I
Processor Reset Input Bus Request Input Bus Grant Output Bus Grant Hung Output Data Memory Select Output Program Memory Select Output Memory Select Output Byte Memory Select Output Combined Memory Select Output Memory Read Enable Output Memory Read Enable Output Edge- or Level-Sensitive Interrupt Request1
Level-Sensitive Interrupt Requests1
PF0 (Mode A) 1 CLKIN, XTAL CLKOUT SPORT0 SPORT1 IRQ1:0 F1, F0 PWD PWDACK FL0, FL1, FL2 VDD AND GND EX-Port 2 1 5 5
1 1 3 16
I O O I
1 1
I I I/O I
Level-Sensitive
Interrupt Requests1
9
I/O
For Emulation Use
PF3 1 PF2 (Mode C) 1
PF1 (Mode B) 1
I
Edge-Sensitive Interrupt Requests1 Programmable I/O Pin Programmable I/O Pin Mode Select Input-Checked only During RESET Mode Select Input-Checked only During RESET
NOTES 1 Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag. 2 SPORT configuration determined by the DSP System Control Register. Software configurable.
-4-
REV. 0
ADSST-EM-3035
100-Lead TQFP Package Pinout
93 PF1 [MODE B] 89 PF2 [MODE C] 94 PF0 [MODE A]
100 A3/IAD2 99 A2/IAD1
96 PWDACK
98 A1/IAD0
91 PWD
92 GND
80 GND 79 D19
95 BGH
90 VDD
88 PF3
84 D23
83 D22
78 D18
77 D17
A4/IAD3 A5/IAD4 GND A6/IAD5 A7/IAD6 A8/IAD7 A9/IAD8 A10/IAD9 A11/IAD10
1 2 3 4 5 6 7 8 9
PIN 1 IDENTIFIER
76 D16
81 D20
82 D21
86 FL1 85 FL2
87 FL0
97 A0
75 D15 74 D14 73 D13 72 D12 71 GND 70 D11 69 D10 68 D9 67 VDD 66 GND 65 D8 64 D7/IWR 63 D6/IRD 62 D5/IAL 61 D4/IS 60 GND 59 VDD 58 D3/IACK 57 D2/IAD15 56 D1/IAD14 55 D0/IAD13 54 BG 53 EBG 52 BR 51 EBR
IRQL0+PF5 27 GND 28 IRQL1+PF6 29 IRQ2+PF7 30 DT0 31 TFS0 32 RFS0 33 DR0 34 SCLK0 35 VDD 36 DT1/FO 37 TFS1/IRQ1 38 RFS1/IRQ0 39 DR1/FI 40 GND 41 SCLK1 42 ERESET 43 RESET 44 EMS 45 EE 46 ECLK 47 ELOUT 48 ELIN 49 IRQE+PF4 26 EINT 50
A12/IAD11 10 A13/IAD12 11 GND 12 CLKIN 13 XTAL 14 VDD 15 CLKOUT 16 GND 17 VDD 18 WR 19 RD 20 BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25
ADSST-2185KST-133
TOP VIEW (Not to Scale)
REV. 0
-5-
ADSST-EM-3035
System Interface Clock Signals
Figure 2 shows typical basic system configurations with the ADSST-2185KST-133, two serial devices, a byte-wide EPROM and optional external program and data overlay memories (mode selectable). Programmable wait state generation allows the processor to connect easily to slow peripheral devices. The ADSST2185KST-133 also provides four external interrupts and two serial ports, or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to a single address bit (A0). Additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals.
FULL MEMORY MODE
Either a crystal or a TTL-compatible clock signal can clock the ADSST-2185KST-133. The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency during normal operation. The only exception is while the processor is in the power-down state. For additional information, refer to Chapter 9, ADSP-2100 Family User's Manual, Third Edition, for detailed information on this power-down feature. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor's CLKIN input. When an external clock is used, the XTAL input must be left unconnected. The ADSST-2185KST-133 uses an input clock with a frequency equal to half the instruction rate; a 20.00 MHz input clock yields a 25 ns processor cycle (which is equivalent to 40 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. Because the ADSST-2185KST-133 includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessorgrade crystal should be used.
CLKIN XTAL CLKOUT
1/2x CLOCK OR CRYSTAL
ADSST-2185 KST-133
CLKIN ADDR13-0 XTAL FL0-2 PF3 IRQ2/PF7 IRQE/PF4 IRQL0/ PF5 IRQL1/ PF6 MODE C/PF2 MODE B/PF1 MODE A/PF0
14
A13-0 D23-16 A0-A21
24 DATA23-0 BMS
D15-8 DATA CS A10-0 ADDR D23-8 CS A13-0
BYTE MEMORY
DATA (PERIPHERALS) IOMS 2048 LOCATIONS
I/O SPACE
SPORT1
SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI D23-0 PMS DMS CMS BR BG BGH PWD PWDACK
ADDR DATA
OVERLAY MEMORY
TWO 8K PM SEGMENTS TWO 8K DM SEGMENTS
SPORT0
SERIAL DEVICE SCLK0 RFS0 TFS0 DT0 DR0
DSP
HOST MEMORY MODE
Figure 3. External Crystal Connections
ADSST-2185 KST-133
1/2x CLOCK OR CRYSTAL CLKIN ADDR0 XTAL FL0-2 PF3 IRQ2/PF7 IRQE/PF4 IRQL0/ PF5 IRQL1/ PF6 MODE C/PF2 MODE B/PF1 MODE A/PF0 DATA23-8 BMS 16 1
A clock output (CLKOUT) signal is generated by the processor at the processor's cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register.
Reset
SPORT1
SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI
IOMS
SPORT0
SERIAL DEVICE SCLK0 RFS0 TFS0 DT0 DR0
PMS DMS CMS BR BG BGH PWD PWDACK
IDMA PORT
SYSTEM INTERFACE OR CONTROLLER
16
IRD/D6 IWR/D7 IS/D4 IAL/D5 IACK/D3 IAD15-0
Figure 2. Basic System Interface
Recommended Operating Conditions Parameters VDD Supply Voltage TAMB Ambient Operating Temperature A Grade Min Max 4.5 0 5.5 +70 B Grade Min Max 4.5 -40 5.5 +85 Unit V C -6-
The RESET signal initiates a master reset of the ADSST2185KST-133. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this powerup sequence, the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, tRSP. The RESET input contains some hysteresis; however, if you use an RC circuit to generate your RESET signal, the use of an external Schmidt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. REV. 0
ADSST-EM-3035 ELECTRICAL CHARACTERISTICS
Parameters VIH VIH VIL VOH High-Level Input Voltage High-Level CLKIN Voltage Low-Level Input Voltage1, 3 High-Level Output Voltage1, 4, 5
1, 2
Test Conditions @ VDD = max @ VDD = max @ VDD = min @ VDD = min IOH = -0.5 max @ VDD = min IOH = -100 A6 @ VDD = min IOL = 2 mA @ VDD = max VIN = VDD max @ VDD = max VIN = 0 V @ VDD = max VIN = VDD max @ VDD = max VIN = 0 V8 @ VDD = 5.0 @ VDDINT = 5.0 TAMB = 25C tCK = 30 ns11 tCK = 25 ns11 @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25C @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25C
Min 2.0 2.2
K/B Grade Typ
Max
Unit V V V V V V A A A A mA
0.8 2.4 VDD - 0.3 0.4
VOL IIH IIL IOZH IOZL IDD IDD
Low-Level Output Voltage1, 4, 5 High-Level Input Current3 Low-Level Input Current3 Three-State Leakage Current7 Three-State Leakage Current7 Supply Current (Idle)9 Supply Current (Dynamic)10, 11
10 10 10 10 12.4
55 [65]
mA mA
CI CO
Input Pin Capacitance3, 6, 12 Output Pin Capacitance6, 7, 12, 13
8
pF
8
pF
NOTES 1 Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7. 2 Input only pins: RESET, BR, DR0, DR1, PWD. 3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH. 5 Although specified for TTL outputs, all ADSST-2185KST-133 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads. 6 Guaranteed but not tested. 7 Three-statable pins: A0-A13, D0, D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0, PF7. 8 0 V on BR, CLKIN inactive. 9 Idle refers to ADSST-2185KST-133 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND. 10 IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 11 VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section. 12 Applies to TQFP package type 13 Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
ENVIRONMENTAL CONDITIONS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7.0 V Input Voltage . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range (Ambient) . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . 280C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Rating: TAMB = TCASE - (PD CA) TCASE = Case Temperature in C PD = Power Dissipation in W JA = Thermal Resistance (Junction-to-Ambient) JC = Thermal Resistance (Junction-to-Case) CA = Thermal Resistance (Case-to-Ambient) Package TQFP
JA JC CA
50C/W
2C/W
48C/W
REV. 0
-7-
ADSST-EM-3035
ADSST-73360AR (ADC) FEATURES Six 16-Bit A/D Converters Programmable Input Sample Rate Simultaneous Sampling 76 dB SNR 64 kS/s Maximum Sample Rate -83 dB Crosstalk Low Group Delay (125 s Typ per ADC Channel) Programmable Input Gain Flexible Serial Port which Allows Multiple Devices to be Connected in Cascade Single (2.7 V to 5.5 V) Supply Operation 80 mW Max Power Consumption at 2.7 V On-Chip Reference 28-Lead SOIC GENERAL DESCRIPTION
The ADSST-73360AR is a six-input channel analog front-end processor for power metering. It features six 16-bit A/D conversion provide 76 dB signal-to-noise ratio over a dc to 4 kHz signal bandwidth. Each channel also features a programmable input gain amplifier (PGA) with gain settings in eight stages from 0 dB to 38 dB. The ADSST-73360AR is particularly suitable for industrial power metering as each channel samples synchronously, ensuring that there is no (phase) delay between the conversions. The ADSST-73360AR also features low group delay conversions on all channels. An on-chip reference voltage is included with a nominal value of 1.2 V. The sampling rate of the device is programmable with four separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz sampling rates (from a master clock of 16.384 MHz). A serial port (SPORT) allows easy interfacing of single or cascaded devices to industry standard DSP engines. The SPORT transfer rate is programmable to allow interfacing to both fast and slow DSP engines. The ADSST-73360AR is available in 28-lead SOIC.
VINP1 SIGNAL CONDITIONING VINN1 0/38dB PGA
ANALOG CONDITIONING
DECIMATOR
SDI SDIFS
VINP2 SIGNAL CONDITIONING VINN2 0/38dB PGA
ANALOG CONDITIONING
SCLK DECIMATOR
VINP3 VINN3 REFCAP REFOUT VINP4
SIGNAL CONDITIONING
0/38dB PGA
ANALOG CONDITIONING
DECIMATOR RESET
REFERENCE
ADSST-73360AR
SERIAL I/O PORT
MCLK SE
SIGNAL CONDITIONING VINN4
0/38dB PGA
ANALOG CONDITIONING
DECIMATOR
VINP5 VINN5
SIGNAL CONDITIONING
0/38dB PGA
ANALOG CONDITIONING
DECIMATOR SDO SDOFS
VINP6 VINN6
SIGNAL CONDITIONING
0/38dB PGA
ANALOG CONDITIONING
DECIMATOR
Figure 4. Functional Block Diagram
-8-
REV. 0
ADSST-EM-3035
SPECIFICATIONS
ADSST-73360AR
(AVDD = 5 V
Parameter
REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, VREFOUT Minimum Load Resistance Maximum Load Capacitance ADC SPECIFICATIONS Maximum Input Range at VIN2, 3 Nominal Reference Level at VIN (0 dBm0) Absolute Gain PGA = 0 dB PGA = 38 dB Gain Tracking Error Signal to (Noise + Distortion) PGA = 0 dB PGA = 38 dB Total Harmonic Distortion PGA = 0 dB PGA = 38 dB Intermodulation Distortion Idle Channel Noise Crosstalk ADC-to-ADC DC Offset Power Supply Rejection Wave Group Delay4, 5 2 100 3.156 3.17 2.1908 0 +0.1 -0.5 0.1 76 70 -86 -80 -79 -76 -85 20 -55 25 50 95 190 25
10%; DVDD = 5 V
10%; DGND = AGND = 0 V, fMCLK = 16.384 MHz, fSCLK = 8.192 MHz, fS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted1.)
Min Typ Max Unit Test Conditions/Comments
1.25 2.5 50 130 1.25 2.5
V V ppm/C V V k pF V p-p dBm V p-p dBm dB dB dB dB dB dB dB dB dB dB mV dB s s s s k6
5 VEN = 0 5 VEN = 1 0.1 F Capacitor Required from, REFCAP to AGND2
5 VEN = 0, Unloaded 5 VEN = 1, Unloaded 5 VEN = 1
5 VEN = 1, Measured Differentially 5 VEN = 1, Measured Differentially
1.0 kHz 1.0 kHz 1.0 kHz, +3 dBm0 to -50 dBm0 0 Hz to fS/2; fS = 8 kHz 0 Hz to 4 kHz; fS = 64 kHz
Input Resistance at VIN 2, 4 FREQUENCY RESPONSE (ADC)7 Typical Output Frequency (Normalized to f S) 0 0.03125 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 > 0.5
PGA = 0 dB PGA = 0 dB ADC1 Input Signal Level: 1 kHz, 0 dBm0 ADC2 Input at Idle PGA = 0 dB Input Signal Level at AVDD and DVDD Pins 1.0 kHz, 100 mV p-p Sine 64 kHz Output Sample Rate 32 kHz Output Sample Rate 16 kHz Output Sample Rate 8 kHz Output Sample Rate DMCLK = 16.384 MHz
0 -0.1 -0.25 -0.6 -1.4 -2.8 -4.5 -7.0 -9.5 < -12.5
dB dB dB dB dB dB dB dB dB dB
REV. 0
-9-
ADSST-EM-3035
Parameter
LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IIH, Input Current CIN, Input Capacitance LOGIC OUTPUT VOH, Output High Voltage VOL, Output Low Voltage Three-State Leakage Current POWER SUPPLIES AVDD1, AVDD2 DVDD IDD8
Min
VDD - 0.8 0
Typ
Max
VDD 0.8
Unit
V V A pF V V A V V
Test Conditions/Comments
-0.5 10 VDD - 0.4 0 -0.3 4.5 4.5 5.5 5.5 VDD 0.4
|IOUT| < 100 A |IOUT| < 100 A
See Table II
NOTES 1 Operating temperature range is as follows: -40C to +85C. Therefore, TMIN = -40C and TMAX = +85C. 2 Test conditions: Input PGA set for 0 dB gain (unless otherwise noted). 3 At input to sigma-delta modulator of ADC. 4 Guaranteed by design. 5 Overall group delay will be affected by the sample rate and the external digital filtering. 6 The ADCs input impedance is inversely proportional to DMCLK and is approximated by: (4 10")/DMCLK. 7 Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of -10 dBm0), with 38 dB preamplifier bypassed and input gain of 0 dB. 8 Test Conditions: no load on digital inputs, analog inputs ac coupled to ground. Specifications subject to change without notice.
Table II. Current Summary (AVDD = DVDD = 3.3 V)
Conditions ADCs Only On REFCAP Only On REFCAP and REFOUT Only On All Sections Off All Sections Off
Analog Current 16 0.8 3.5 0.1 0
Digital Current 16 0 0 1.9 0.05
Total Current (Max) 32 0.8 3.5 2.0 0.06
SE 1 0 0 0 0
MCLKON ON YES NO NO YES NO
Comments REFOUT Disabled REFOUT Disabled MCLK Active Levels Equal to 0 V and DVDD Digital Inputs Static and Equal to 0 V and DVDD
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C unless otherwise noted.)
AVDD, DVDD to GND . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . . -0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND . . . . . . -0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C SOIC, JA Thermal Impedance . . . . . . . . . . . . . . . . . . 75C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSST-EM-3035 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-10-
REV. 0
ADSST-EM-3035
PIN CONFIGURATION
VINP2 1 VINN2 2 VINP1 3 VINN1 4 REFOUT 5 REFCAP 6 AVDD2 DGND
7 28 27 26 25
VINN3 VINP3 VINN4 VINP4 VINN5 VINP5
ADSST73360AR
24 23 22
VINN6 TOP VIEW (Not to Scale) 21 VINP6 AGND2 8
9 20 19 18 17 16 15
AVDD1 AGND1 SE SDI SDIFS SDOFS
DVDD 10 RESET 11 SCLK 12 MCLK 13 SDO 14
PIN FUNCTION DESCRIPTIONS
Mnemonic VINP1 VINN1 VINP2 VINN2 VINP3 VINN3 VINP4 VINN4 VINP5 VINN5 VINP6 VINN6 REFOUT Function Analog Input to the Positive Terminal of Input Channel 1 Analog Input to the Negative Terminal of Input Channel 1 Analog Input to the Positive Terminal of Input Channel 2 Analog Input to the Negative Terminal of Input Channel 2 Analog Input to the Positive Terminal of Input Channel 3 Analog Input to the Negative Terminal of Input Channel 3 Analog Input to the Positive Terminal of Input Channel 4 Analog Input to the Negative Terminal of Input Channel 4 Analog Input to the Positive Terminal of Input Channel 5 Analog Input to the Negative Terminal of Input Channel 5 Analog Input to the Positive Terminal of Input Channel 6 Analog Input to the Negative Terminal of Input Channel 6 Buffered Reference Output, which has a nominal value of 1.2 V or 2.4 V, the value being dependent on the status of Bit 5 VEN (CRC:7). This pin can be overdriven by an external reference if required. A Bypass Capacitor to AGND2 of 0.1 F is required for the on-chip reference. The capacitor should be fixed to this pin. Analog Power Supply Connection Analog Ground/Substrate Connection Digital Ground/Substrate Connection Digital Power Supply Connection AGND1 AVDD1 SDI SDOFS MCLK SDO Mnemonic RESET Function Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital circuitry. Output Serial Clock whose rate determines the serial transfer rate to/from the ADSST73360AR. It is used to clock data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (MCLK) divided by an integer number This integer number being the product of the external master clock rate divider and the serial clock rate divider. Master Clock Input. MCLK is driven from an external clock signal. Serial Data Output of the ADSST-73360AR. Both data and control information may be output on this pin and are clocked on the positive edge of SCLK. SDO is in threestate when no information is being transmitted and when SE is low. Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in three-state when SE is low. Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low. Serial Data Input of the ADSST-73360AR. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low. SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original values (before SE was brought low. However, the timing counters and other internal registers are at their reset values. Analog Ground Connection Analog Power Supply Connection
SCLK
SDIFS
REFCAP
SE
AVDD2 AGND2 DGND DVDD
REV. 0
-11-
ADSST-EM-3035
Grounding and Layout
ANALOG GROUND
and DGND respectively, with 0.1 F ceramic capacitors in parallel with 10 F tantalum capacitors. To achieve the best from these decoupling capacitors, they should be placed as close as possible to the device, ideally right up against it. In systems where a common supply voltage drives both the AVDD and DVDD of the ADSST-73360AR, it is recommended that the system's AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the ADSST-73360AR and AGND and the recommended digital supply decoupling capacitors between the DVDD pin and DGND. NOTE: FOR MORE DETAILS ON ADSST-73360AR, PLEASE REFER TO DATA SHEET OF AD73360
Interfaces between ADSST-EM-3035 and Microcontroller Overview
DIGITAL GROUND
Figure 5. Grounding and Layout
Since the analog inputs to the ADSST-73360AR are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The analog and digital supplies of the ADSST-73360AR are independent and separately pinned out to minimize coupling between analog and digital sections of the device. The digital filters on the encoder section will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital filters also remove noise from the analog inputs provided the noise source does not saturate the analog modulator. However, because the resolution of the ADSST73360LAR ADC is high, and the noise levels from the ADSST-73360AR are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the ADSST-73360AR should be designed so the analog and digital sections are separated and confined to certain sections of the board. The ADSST-73360AR pin configuration offers a major advantage in that its analog and digital interfaces are connected on opposite sides of the package. This facilitates the use of ground planes that can be easily separated, as shown in Figure 5. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place. If this connection is close to the device, it is recommended to use a ferrite bead inductor as shown in Figure 5. Avoid running digital lines under the device for they will couple noise onto the die. The analog ground plane should be allowed to run under the ADSST-73360AR to avoid noise coupling. The power supply lines to the ADSST-73360AR should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply lines. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A micro-strip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. Good decoupling is important when using high speed devices. All analog and digital supplies should be decoupled to AGND
The following paragraphs describe the interface between the ADSST-EM-3035 chipset and the microcontroller. The sequence of operations is a critical issue for proper functioning of the two processors on the board. The DSP processor is primarily used to compute various parameters, provide the impulse outputs on the external LEDs and provide automatic gain switching inside the ADC. The microcontroller can collect the data from the chipset for data management for further processing. There are two basic functions that the microcontroller performs in a handshaking mode with the DSP processor:
* Boot loading the DSP with metering software on power up
(for non-ROM coded version only)
* Communication with the DSP on SPI to:
Send Initialization data on power up after boot loading the DSP with metering software Receive data from DSP during normal operation Receive and send data during calibration This section describes the Boot loading and SPI operations.
BOOT LOADING THE DSP PROCESSOR FROM THE MICROCONTROLLER
The DSP processor has an internal program memory RAM that supports boot loading. With boot loading, the processor reads instructions from a byte-wide data bus connected to the microcontroller and stores the instructions in the 24-bit wide internal program memory. The host microcontroller, is the source of bytes to be loaded into on-chip memory. The choice of which technique to use depends upon the I/O structure of the host microcontroller, availability of I/O port lines, and the amount of address decoding logic already available in the system. The description here is one of the many ways that this could be configured. However, the software on the microcontroller has been written in way to make optimum use of the configuration. Figure 6 illustrates the system implementation to allow a microcontroller to boot the DSP processor. The only hardware required is a D-type flip-flop and a 5 k resistor. The resistor is used to pull the DSP processor's BMS pin (Boot Memory Select) high. The DSP processor boots using the BDMA option. The BDMA option can be used when pins Mode A, Mode B, and Mode C on the DSP are tied low. With these pins tied low the DSP automatically enters its boot sequence after the processor is reset.
-12-
REV. 0
ADSST-EM-3035
In the sequence of booting the DSP, it has to be loaded with an object code into the internal program memory. The byte wide memory boot code file has the following structure: a) 32 words or 96 bytes of the initial header, b)81 words or 243 bytes for initializing BDMA and associated registers, c) 6712 words or 20136 bytes of program code.
VDD C 5k
program code, it will overwrite the first 113 words (i.e., 339 bytes). After reading 20136 bytes, it will start execution automatically. The process of loading the code to the DSP is as follows: * After the microcontroller is reset, hold DSP in reset by bringing reset pin low. * Make PX high and clock PY (low to high transition). This will make BR low. In effect, the DSP will not read because it has granted its buses since BR is asserted. * Put the first byte of the program code on the DSP bus D8 to D15 and deassert BR, which is done by taking PX low and clocking a transition on PY (low to high). Since the DSP buses have been released, it will read the byte and assert BMS. The assertion of BMS will cause the flip-flop to preset (PR on 74LS74) itself and therefore BR is again asserted. * Continue this process byte by byte for 96 bytes and give a small delay. * After the delay continue the byte loading process for the next 243 bytes and give a small delay again. * Continue the byte loading process for 20136 bytes. * Soon after the last program byte is loaded, the DSP starts execution of the code. At the start of execution, the DSP waits for uploading of 154 bytes of data consisting of calibration constants (gain & dc offsets), E-pulse constants and filter coefficients. This data has to be sent to the DSP processor on the SPI port. Until the DSP receives the 154 bytes, the actual process of executing the metering code on the DSP does not start. Soon after receiving all the constants (i.e. 154 bytes) the metering process starts. Four dummy bytes have to be sent after the start of execution for the DSP to send back the check sum of its internal code. The microcontroller can use this to verify that the complete metering code has been loaded on the DSP processor properly. The DSP is now ready to provide the computed data on the SPI port.
DSP
BMS
PX
D
PR 74L574
PY PZ
CLK
O
BR RESET
D0-D7 D0-D7 CLOCK
D0-D7 FLASH
D8-D15
Figure 6. System Architecture for Boot Loading DSP Processor From Microcontroller
When the DSP is reset with the pins Mode A, Mode B, and Mode C tied low, it enters into the byte wide memory data access mode. The boot loading process will consist of the DSP reading the first 32 words, a small delay, say one millisecond for it execute these 32 words of program. The DSP will then read the next 81 words. After which a small delay, of say one millisecond, will be required for it to execute these 81 words. The DSP will now (with BDMA registers initialized) read the code length also initialized in the previous process. It should be noted that when the DSP reads the 20136 bytes from its port of the
1ST BYTE OF DATA DATA D0-D7 T1 PIN BOOT 1 MINIMUM 6 DSP CLOCK CYCLES
PIN BOOT 2
BR BMS
Figure 7. Timing Diagram for Boot Loading the DSP Processor
REV. 0
-13-
ADSST-EM-3035
SERIAL PERIPHERAL INTERFACE (SPI) AND CONTROL
The DSP and the microcontroller are interfaced through Serial Peripheral Interface (SPI). The microcontroller is always configured as a master and the DSP as a slave.
FRAMING SIGNAL RFS DSP CONTROL TF
data train. The data received from the DSP will be in the same sequence as described in Table IV. If the microcontroller does not require all the parameters then it may stop sending dummy bytes at any time. The diagram below shows the sequence of operation.
FRAMING SIGNAL
DR
SPI TRANSMIT SPI RECEIVE
CLOCK
DT
SCLK
CLK
DATA
Figure 9. SPI Sequence of Operation
FL2 DSP INTERRUPT MICROCONTROLLER
Quadrant and Other Conventions
The data sent by the DSP is based on the following convention:
Figure 8. Serial Peripheral Interface and Control
SPI OPERATION
There are two modes of communication between DSP and microcontroller.
* * * *
Figure 10 gives the quadrant convention used by the chipset. Import means delivered from the utility to the user. Export means delivered by the user to the utility. Total means total of all three phases.
- REACTIVE ACTIVE EXPORT ACTIVE IMPORT
* Microcontroller to DSP (while uploading the initial data of
154 bytes, including four bytes to read checksum of code from DSP, and sending a command) Bring the DSP_control pin low, i.e., give a high to low transition. This informs the DSP that the data after this transition is a valid data. Send the data byte on the microcontroller's SPI port. Since the microcontroller is configured as a master, the clock signal will be generated by the microcontroller and the DSP being a slave will read the data byte in sync with the clock signal. Bring DSP_control signal back to high state.
CAPACITIVE
Q2
Q1
Q3
Q4
* DSP to Microcontroller (while transmitting computed data
to the microcontroller) The DSP during its metering code execution, is ready to give the computed parameters to the microcontroller after every 32 cycles of power line. To request data from the DSP, the microcontroller sends a request code 45h on the SPI bus. The DSP then sends a high to low transition on Pin FL2 soon after it completes the next 32 cycles of computation as an indication to the microcontroller that it is ready to transmit most recent data. Since the microcontroller is a master, it has to now send clock signal to the DSP on the SPI to receive data. For the clock signal to be generated, the microcontroller has to send a dummy byte. The dummy byte (say, 0xFF) should be one that is not recognized by the DSP as a command. The microcontroller may send as many dummy bytes as it requires up to a maximum of 522 bytes for the complete
Power Up Initialization
+ REACTIVE INDUCTIVE
Figure 10.
To reduce the component count, cost and to give designer a greater flexibility in designing, ADSST-EM-3035 has not been provided with any Nonvolatile Memory to store the calibration constants and initialization data. On power up, after the boot loading of the DSP software, the microcontroller provides the DSP with all the initialization data. After receiving the initialization data the DSP starts the metering. The table below list outs the data that has to be transferred to the DSP on power up.
-14-
REV. 0
ADSST-EM-3035
Table III. Data Transfer to DSP on Power-Up Data from DSP to Microcontroller
Initialization Gain Constants and DC Offsets R Phase Voltage Gain Y Phase Voltage Gain B Phase Voltage Gain R Phase Current Low Gain Y Phase Current Low Gain B Phase Current Low Gain R Phase Current High Gain Y Phase Current High Gain B Phase Current High Gain R Phase Voltage DC Offset Y Phase Voltage DC Offset B Phase Voltage DC Offset R Phase Current Low Gain DC Offset Y Phase Current Low Gain DC Offset B Phase Current Low Gain DC Offset R Phase Current High Gain DC Offset Y Phase Current High Gain DC Offset B Phase Current High Gain DC Offset E-pulse (Type)* Energy Pulse e = active e1 = Apparent Pulse E-pulse Constant Range from 1,000-20,000 Impulse Constant 1 (pulses/kWh) Pulse E-pulse Constant Range from 1,000-20,000 PHASE COMPENSATION VARIABLES R Phase Coeff for High Current Range
Value Defaults 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4000h 4000h 4000h 4000h 4000h 4000h 4000h 4000h 4000h 0 0 0 0 0 0 0 0 0
To facilitate easy of operation, the data transfer form DSP to microcontroller has been segregated into multiple blocks. Table IV lists the various data blocks:
Table IV. Data Transfer Sequence from DSP to Microcontroller
DATA from DSP on SPI BUS REQUEST CODE 45h R Phase Voltage R Phase Current R Phase Active Power R Phase Apparent Power R Phase Inductive Power R Phase Capacitive Power R Phase Power Factor R Phase Active Energy Import R Phase Apparent Energy R Phase Inductive Energy R Phase Active Energy Export R Phase Capacitive Energy Y Phase Voltage Y Phase Current Y Phase Active Power Y Phase Apparent Power Y Phase Inductive Power Y Phase Capacitive Power Y Phase Power Factor Y Phase Active Energy Import Y Phase Apparent Energy Y Phase Inductive Energy Y Phase Active Energy Export Y Phase Capacitive Energy B Phase Voltage B Phase Current B Phase Active Power B Phase Apparent Power B Phase Inductive Power B Phase Capacitive Power B Phase Power Factor B Phase Active Energy Import B Phase Apparent Energy B Phase Inductive Energy B Phase Active Energy Export B Phase Capacitive Energy Total Active Power Total Apparent Power Total Inductive Power Total Capacitive Power Average Power Factor Total Active Energy Import Total Apparent Energy Total Inductive Energy Total Active Energy Export Total Capacitive Energy Frequency R Phase Channel_Present Y Phase Channel_Present
Byte(s) 1 2 2 4 4 4 4 2 4 4 4 4 4 2 2 4 4 4 4 2 4 4 4 4 4 2 2 4 4 4 4 2 4 4 4 4 4 4 4 4 4 2 4 4 4 4 4 2 1 1
1 2 2 12
1 2000 2000 0000, 0000, 7FFF, 0000, 0000, 0000 -Do-Do-Do-Do-Do-Do-Do-Do-
R Phase Coeff for Middle Current Range R Phase Coeff for Low Current Range Y Phase Coeff for High Current Range Y Phase Coeff for Middle Current Range Y Phase Coeff for Low Current Range B Phase Coeff for High Current Range B Phase Coeff for Middle Current Range B Phase Coeff for Low Current Range
12 12 12 12 12 12 12 12
*The first byte to be sent for initialization is 45h followed by all the above tabled parameters in the same sequence.
Phase Compensation Coefficients
Three sets of filter coefficients have been provided which will be automatically selected by the DSP during execution based on the maximum current (Imax). In the ADSST-EM-3035, the Imax is fixed at 20 Amps. Therefore the current ranges have been grouped as:
* High current range: From 20 Amps to 7 Amps * Middle current range: 7 Amps to 1.5 Amps * Low current range: 1.5 Amps to 0 Amps
REV. 0
-15-
ADSST-EM-3035
DATA from DSP on SPI BUS B Phase Channel_Present R Phase Current Division FlagUnits_flag_R Y Phase Current Division FlagUnits_flag_Y B Phase Current Division FlagUnits_flag_B R Phase Negative Power Flag Y Phase Negative Power Flag B Phase Negative Power Flag R Phase (INDUC/CAP POWER Flag) Y Phase (INDUC/CAP POWER Flag) B Phase (INDUC/CAP POWER Flag) GAIN CONTRASTS AND DC OFFSETS R Phase Voltage Gain Y Phase Voltage Gain B Phase Voltage Gain R Phase Current Low Gain Y Phase Current Low Gain B Phase Current Low Gain R Phase Current High Gain Y Phase Current High Gain B Phase Current High Gain R Phase Voltage DC Offset Y Phase Voltage DC Offset B Phase Voltage DC Offset R Phase Current Low Gain DC Offset Y Phase Current Low Gain DC Offset B Phase Current Low Gain DC Offset R Phase Current High Gain DC Offset Y Phase Current High Gain DC Offset B Phase Current High Gain DC Offset DC_Offset Calibration Done (EFh) Total Negative Power Flag Total Inductive Capacitive Flag HARMONIC ANALYSIS DATA (All odd harmonics sequenced from fundamental to 21st order, total 11 harmonics of 2 bytes each) R Phase Voltage Components Magnitude R Phase Current Components Magnitude R Phase Voltage Components Phase R Phase Current Components Phase Y Phase Voltage Components Magnitude Y Phase Current Components Magnitude Y Phase Voltage Components Phase Y Phase Current Components Phase B Phase Voltage Components Magnitude B Phase Current Components Magnitude B Phase Voltage Components Phase B Phase Current Components Phase 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 Byte(s) 1 1 1 1 1 1 1 1 1 1
Table V. Interpretation of the Voltage Data
Phase Voltage Data from DSP Hex (2 byte) 5A10h Decimal 23056 Voltage 230.56 V
Table VI. Interpretation of the Current Data
Line Current Data from DSP Hex (2 Byte) Decimal 278Bh 278Bh 10123 10123
Unit flag_X (X = R/Y/B) 1 0
Current 1.0123 A 10.123 A
Frequency Data from DSP
The frequency data is with two decimal places. This means that the value has to be divided by 100 to get the frequency. For example, if DSP data = 139Fh (decimal value = 5023), then the frequency is 50.23 Hz
Interpretation of the Power Data
As in the case of current and voltages, described above, all the power data supplied by DSP has to be interpreted, as shown in Table VII. The data received from the DSP is in a 4-byte format. The least significant word comes first and the most significant word comes last, e.g., 000D1C4A will come as 1C4A000D and this word reversal has to be performed by the controller.
Table VII. Interpretation of the Power Data
Power Data from DSP Hex (4-Byte) 000D1C4A Decimal 859210 Power 859.210 W
Interpretation of the Power Factor Data
2 11 = 22 22 22 22 22 22 22 22 22 22 22 22
The DSP data for power factor has a resolution up to four decimal places. To get the value of Power Factor the DSP data has to be divided by 10,000.
Table VIII. Interpretation of the Power Factor Data
Power Factor Data from DSP Hex (2-Byte) Decimal 1388h 5000 Power Factor 0.5
Interpretation of the Energy Data
The DSP data for energy has a resolution up to four decimal places. To get the value of Energy the DSP data has to be divided by 10,000.
Table IX. Interpretation of the Energy Data
Energy Data from DSP Hex (4-Byte) 000D1C4Ah Decimal 859210 Energy 85.9210 kWh
-16-
REV. 0
ADSST-EM-3035
Interpretation of Harmonics Data
Each harmonic data from DSP is two byte wide. The voltage and phase angle values have a resolution of up to second decimal place and the current has up to third decimal place.
INPUT SECTION
PHASE VOLTAGE 1M 100 0.001 F TO ADC
The reference design has a CT with turn ratio of 1:2500 and burden resistance of 82 . This generates 0.656 V rms or 0.928 V (0-pk) at 20 amps current. This leaves enough margins for current pulses or low crest factor loads, such as electronic loads such as SMPS. The maximum current can be up to 32.767 amps.
CALIBRATION
3.3k NEUTRAL
GND LINE CURRENT 100
PDSP TO ADC
ADSST-EM-3035 Chipset has a highly advance calibration routines embedded into the software. Easy of calibration is the philosophy in ADSST-EM-3035 Chipset. ADSST-EM-3035 chipset enables dc offset and gain computation on the voltage and current channels and also performs phase and nonlinearity compensation on the current transformer. Calibrations for power is done internally and no extra procedure is required for it. This section describes the calibration procedure required.
Voltage Gain Calibration
82
0.01 F GND VCC
To calibrate voltage channel:
*VALUE MAY CHANGE ACCORDING
* Inject a known voltage (VI ) to the meter based on ADSSTEM-3035
Figure 11. Input Section
ADSST-73360AR has an input range of VREF + (VREF 0.6525) to VREF - (VREF 0.6525) V p-p (0.856 V to 4.14 V for 2.5 V VREF). This limit defines the resistance network on the potential circuits and the burden resistance on the secondary side of the CT. ADSST-73360AR being a unipolar ADC the ac, potential, and current have to be offset by a desired dc level. The reference design has a dc offset of 2.5 V. This limits the p-p signal range of potential and current to 1.64 V peak or 1.16 V rms. For details please refer to the data sheet of AD73360.
Potential Section
* Note the voltage read by meter say VM * Voltage gain coefficient = (VI/VM) 0x4000. * The calculated coefficients are to be communicated to the
microcontroller for storage.
* Repeat the same procedure for all the three channels * Note: Where 0x4000 is default coefficient in hex
Current Gain Calibration
The selection of potential divider circuit should be such that it can:
The Current Gain calibration is performed at two current settings to compute two current gain coefficients, namely current high gain and current low gain coefficients. In all six current gain coefficients are calculated for all the three phase currents. The gains are calculated at:
* Handle high surge voltages * Should have minimum VA burden * Give approximately 0.656 V rms output at nominal voltage
such that it sufficiently takes care of over voltage.
* I1 = 20 A * I2 = 5 A
Inject the meter with current value I1 Note the value of the current sent by meter (IM) Current low gain coefficient = (I1/IM) Inject the meter with I2 current Note the value of the current sent by meter (IM) Current high gain coefficient = (I2/IM) 0x4000 The calculated coefficients are to be communicated to the microcontroller for storage Repeat the procedure for other Phases
DC Offset Calibration for Voltage and Current
* The reference design has 1 M and 3.3 k resistance
network.
Current Section
0x4000
The selection of CT ratio and burden resistance should be such that it can
* Handle the complete dynamic range for the current signal input. * Give around 1 V(0-pk) output at maximum current such that
it sufficiently takes of loads with low crest factors and current surges.
Writing EFh to DSP on SPI initiates the dc offset calibration in the DSP. After 32 cycles the DSP returns back the offset values and sends FEh as a mark of completion on the SPI. The microcontroller has to store the dc offset constants for uploading during power up.
REV. 0
-17-
ADSST-EM-3035
Table X. DC Offset Calibration Data
* Calculate the normalized lag value (LA, LB, LC) for each phase
as under :
DC-Offset Calibration Offset Calibration (All Three Phases)
Command from Microcontrolled in Hex 0xEF
Setup Input Voltage and Current V = Nominal Voltage I=0
LA =
LB =
60 - PA +2 1.20
60 - PB +2 1.20
(1)
(2)
The microcontroller now issues 0x45H command on SPI to the DSP. The DSP sends back Table IV. This table will contain new dc-offset coefficients. The microcontroller should store these coefficients.
Procedure
LC =
60 - PC +2 1.20
(3)
* Power up the meter with nominal voltage * Give command for calculation of the coefficient (EFh) to
DSP on SPI.
* Run ADSSTCOMP.EXE on PC * Feed the normalized lag value during the execution of
ADSSTCOMP.EXE.
* The ADSSTCOMP.EXE will provide six coefficients for each
phase and the size of each coefficient is 2 bytes.
* Receive the coefficient by sending Ox45 on SPI after waiting
at least 1s.
* The phase compensation should be performed for the three
currents on each phase. These coefficients must be stored in a suitable location such that DSP can get these coefficients on power up in the same sequence as shown in Table III.
Configuration of Output E-pulses
* Store the coefficient
Phase Compensation
The ADSST-EM-3035 employs a patent pending algorithm for phase compensation and non-linearity. This also reduces the cost of the end product by reducing the cost of the sensing elements i.e., CT. To compensate for the phase non-linearity in CTs, the compensation is performed at three current ranges. The three current ranges for calibration are:
The ADSST-EM-3035 Chipset provides two pulse outputs
* 20 A > I1 > 7 A * 7 A > I2 > 1.5 A * 1.5 A > I3 > 0 A
Procedure
* Configurable for Active energy or Apparent energy * Reactive energy * Table III gives the default conditions and configuration for
first E-pulse.
* The E-pulse constant is variable from 1,000 pulses/kWh to
20,000 pulses/kWh.
* The ADSSTCOMP.EXE supplied with the chipset is an
executable file for calculation of the phase compensation coefficients.
* Example: To set 1,500 pulses/kWh, the new E-pulse constant will be 1,500
Inaccuracy of the E-pulse
* Set the voltage equal to 230 V which is the nominal voltage at
all phases.
* Inject I1 current at 0.5 inductive (60 lagging) in all phases. * The chipset performs the harmonic analysis by providing
information about the magnitude and phase angle for all odd harmonics sequenced from fundamental to 21st order. The DSP sends the phase angle information along with other data as described in Table IV after sending the command 0x45.
Higher E-pulse constant is always desirable as it reduces the testing time. However, increase in pulses/kWh may increases the error at higher power. The error can be calculated by the given formula.
General Note About Calibration
* It should be noted that ADSST-EM-3035 does not have any
permanent memory and hence all the calibration data are to be stored by the microcontroller and provided to the DSP at the time of power up.
* The value of the phase angle for line current A, B, and C is
available at the locations 283, 371, and 459 respectively (say PA, PB, PC) in the data stream sent by the DSP.
* Before starting the calibration the meter should be supplied with
the default calibration constants as specified in the Table III.
-18-
REV. 0
ADSST-EM-3035
* The whole calibration can be done in very few steps as shown
in the example below. Start meter with nominal voltage and calculate dc offset Set current at 20 A and calculate voltage gain and low current gain for all channels Set current at 5 A and calculate low current gain for all channels Set current at 20 A < I < 7 A and perform phase compensation for all channels Set current at 1.5 A < I < 7 A and perform phase compensation for all channels Set current at 1.5 A < I < 0 A and perform phase compensation for all channels
MEASUREMENT ACCURACY Overall Accuracy, Power and Energy Measurement
The accuracy figures are measured in nominal conditions unless otherwise indicated. The measurement are taken on the reference design with the given below nominal values.
Reference Design with Metal CT (0.5 Class)
Table XI. Nominal Value: Reference Design Parameters
Parameters Nominal Voltage (Neutral to Line) VN Max Voltage (Neutral to Line) Max Current IMAX Base Current Frequency Power Factor THD of Voltage Temperature
Nominal Value VN = 230 V 1% 300 V IMAX = 20 A In = 5 A FN = 50 Hz/60 Hz 10% 1 < 2% 23 2C
Table XII. Maximum Error (Power and Energies)
Current 0.01 In < I < 0.05 In 0.05 In < I < IMAX 0.02 In < I < 0.1 In 0.1 In < I < IMAX
Voltage VN VN VN VN
PF 1.0 1.0 0.5 Lagging 0.8 Leading 0.5 Lagging 0.8 Leading
Min
Typ 0.1 0.1 0.15 0.15 0.1 0.1
Max 0.2 0.2 0.35 0.35 0.2 0.2
Unit % % % % % %
Table XIII. Unbalanced Load Error
Current 0.05 In < I < IMAX 0.1 In < I < IMAX
Voltage VN VN
PF 1.0 0.5 Lagging
Min
Typ 0.15 0.15
Max 0.2 0.2
Unit % %
Table XIV. Voltage Variation Error
Voltage VN 10% VN 10%
Current 0.05 In < I < IMAX 0.1 In < I < IMAX
PF 1.0 0.5 Lagging
Min
Typ 0.05 0.05
Max 0.1 0.1
Unit % %
Table XV. Frequency Variation Errors
Frequency VN 10% VN 10%
Current 0.05 In < I < IMAX 0.1 In < I < IMAX
PF 1.0 0.5 Lagging
Min
Typ 0.05 0.05
Max 0.1 0.1
Unit % %
REV. 0
-19-
ADSST-EM-3035
Table XVI. Harmonic Distortion Error Table XVIII. Voltage Unbalance Error
Current
Current
Min
Typ
Max
Unit %
Current In
Voltage VN 15
Min
Typ 0.1
Max 0.2
Unit %
10% of Third 0.05 In < I < IMAX Harmonic
0.05 0.1
Table XIX. Starting Current
Voltage Unit % VN
Min
Typ 0.0007
Max 0.001
Unit In
Current 0.1 In
Voltage VN
Min
Typ
Max 0.05
RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS OF ADSST-EM-3035 ABSOLUTE MAXIMUM RATINGS
Parameters VDD Temperature
Ordering Codes
A Grade Min Max 0 7 +70
B Grade Min Max 0 -40 7 +85
Unit V C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V Input Voltage . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C
A Grade: ADSST-EM-3035-BST B Grade: ADSST-EM-3035-KST
ORDERING GUIDE
Model
Temperature Range
Model Included ADSST-2185KST-133 ADSST-73360AR
Package Option SU-100 RW-28
ADSST-EM-3035K 0 to +70C
OUTLINE DIMENSIONS 100-Lead Thin Plastic Quad Flat Package [TQFP] (SU-100)
Dimensions shown in millimeters
0.75 0.60 0.45 SEATING PLANE 1.20 MAX
100 1
28-Lead Standard Small Outline Package [SOIC] Wide Body (RW-28)
Dimensions shown in millimeters and (inches)
16.00 SQ 14.00 SQ
76 75
28 15
18.10 (0.7126) 17.70 (0.6969)
7.60 (0.2992) 7.40 (0.2913)
1 14
TOP VIEW
(PINS DOWN)
10.65 (0.4193) 10.00 (0.3937)
2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039)
25 26 49 50
0.75 (0.0295) 0.25 (0.0098)
45
7 0 0.50 BSC 0.27 0.22 0.17
1.05 1.00 0.95
COPLANARITY 0.10
8 0 1.27 (0.0500) 0.51 (0.0201) SEATING 0.32 (0.0126) BSC 0.33 (0.0130) PLANE 0.23 (0.0091)
1.27 (0.0500) 0.40 (0.0157)
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-026AED-HD CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED
-20-
REV. 0
PRINTED IN U.S.A.
C02740-0-11/02(0)
Table XVII. Reverse Phase Sequence Error

▲Up To Search▲

Price & Availability of ADSST-EM-3035

	To Download ADSST-EM-3035 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .